1. Field of the Invention
The present invention relates generally to a data transmission/reception apparatus and method in a CDMA (Code Division Multiple Access) mobile communication system, and in particular, to a data transmission/reception apparatus and method using united channel coding and rate matching.
2. Description of the Related Art
In a mobile communication system, it is actually impossible to receive a signal transmitted from a transmitter through a wireless network without distortions and noises. Therefore, various techniques for minimizing the distortion and noise have been proposed, and an error control coding technique is a typical proposed techniques. In the latest CDMA mobile communication system, turbo codes and convolutional codes are used for the error control coding technique. An apparatus for the error control coding technique is generally called a “channel encoder.”
FIG. 1 illustrates a structure of a common transmitter in a CDMA mobile communication system. Referring to FIG. 1, N data transport (N Tx) blocks transmitted from an upper layer are provided as an input of a tail bit inserter 110. The tail bit inserter 110 inserts tail bits in each of the N data transport blocks. The tail bit inserter 110, when it utilizes convolutional codes, is arranged preceding a channel encoder 120. However, the tail bit inserter 110, when it utilizes turbo codes, may be included in the channel encoder 120. That is, for the tail bit insertion, a memory in the channel encoder 120 is initialized at a time point where coding in an input data unit is ended. The channel encoder 120 includes at least one code rate in order to encode the N transport blocks. A typical code rate (k/n) is ½ or ¾. In the code rate, k (k=1,3, . . . ) indicates the number of bits of the input data unit applied to the channel encoder 120, and n (n=2,4, . . . ) indicates the number of bits output from the channel encoder 120. Therefore, at a code rate ½, the channel encoder 120 receives, for example, 100 bits and outputs 200 bits, and a code rate ¾, the channel encoder 120 receives, for example, 300 bits and outputs 400 bits. That is, the code rate represents a ratio of the number of bits of the input data unit to the number of coded output bits. In addition, the channel encoder 120 supports a plurality of code rates through puncturing or repetition commonly based on a mother code rate of ⅓ or ⅕. In the case of the mother code rate ⅓, in order to support the code rate ½, the channel encoder 120 generates 300 bits for 100 input bits at the mother code rate ⅓ and then punctures 100 bits from the 300 bits. The channel encoder 120, if it uses the turbo codes, generates systematic bits as an output and parity bits having an error correction capability for the systematic bits. In FIG. 1, the channel encoder 120 determines a code rate to use under the control of a controller 160. Recently, 3GPP (3rd Generation Partnership Project) and 3GPP-2 that have defined the 3rd generation mobile communication standard, have examined the HSDPA (High Speed Data Packet Access) and 1×EV-DV standards for servicing high-speed radio packet data through a shared channel. An adaptive coding and modulation technique is one of the core techniques determined for the standards. This technique adaptively changes the code rate and a modulation order according to a condition of the radio link. In the technique, the controller determines a proper code rate according to a channel condition such that the channel encoder can perform coding at a desired code rate. Such a link adaptation technique can be divided into a power control technique and an AMCS (Adaptive Modulation and Coding Scheme) technique. The power control technique is commonly used in the existing mobile communication system, but the AMCS is used only in an HSDPA mobile communication system.
In the UMTS (Universal Mobile Telecommunications System) standard (Release '99) adopted by the 3GPP, coded bits output from the channel encoder 120 are applied to a rate matcher 130. The rate matcher 130 performs rate matching on the coded bits. Commonly, the number of coded bits output from the channel encoder 120 is not identical to the total number of bits of a transport unit (TU) on the air. The rate matching is an operation of matching the number of coded bits to the total number of bits required on the air through repetition and puncturing on the coded bits. The rate matching is disclosed in detail in the standard adopted by the 3GPP, so an addition description will not be provided. It is expected that the rate matching will be used even in the HSDPA standard.
The coded bits, the number of which is controlled by the rate matcher 130, are applied to an interleaver 140. The interleaver 140 performs interleaving on the coded bits. The interleaving is performed to separate neighboring coded bits as far from one another as possible, thereby maximizing an error correction capability even though a loss occurs in specific data during data transmission over a radio channel. For example, as stated above, since the channel encoder 120 generates systematic bits and parity bits, the neighboring coded bits include systematic bits and associated parity bits. Therefore, when the systematic bits and the parity bits are simultaneously lost, an error correction capability of a channel decoder in a receiver is drastically reduced. For example, in a common radio environment which is affected by fading, a burst error indicating that data bits in a specific position are simultaneously lost occurs frequently. The interleaver 140 performs a function of separating neighboring coded bits as far from one another as possible in order to minimize a data loss due to the burst error.
The interleaved coded bits are applied to a modulator 150. In the HSDPA standard, the interleaved coded bits are modulated by a predetermined one of various modulation techniques such as QPSK (Quadrature Phase Shift Keying), 8PSK (8-ary Phase Shift Keying), 16QAM (16-ary Quadrature Amplitude Modulation) and 64QAM (64-ary Quadrature Amplitude Modulation) before being transmitted. Of the modulation techniques, a high-order modulation technique can transmit more information compared with a low-order modulation technique. However, if it is assumed that the transmitter transmits data at the same power level of the different modulation techniques, a probability of data loss is relatively high when the high-order modulation technique is used as compared to when the low-order modulation technique is used. Therefore, it is necessary to select an optimal modulation technique according to the channel environment. This is controlled by the AMCS controller 160.
FIG. 2 illustrates a detailed structure of the channel encoder 120 shown in FIG. 1. As illustrated in FIG. 2, the channel encoder 120 includes two constituent encoder 212 and 214 with a mother code rate 1/M, an interleaver 210 and a puncturer 216.
Referring to FIG. 2, the first constituent encoder 212 receives a predetermined number of input data bits Xk and outputs coded bits to its output port Yk,1, if a predetermined mother code rate is ⅓. The interleaver 210 interleaves the input data bits Xk. The second constituent encoder 214 encodes the interleaved data bits X′k received from the interleaver 210. If the mother code rate is ⅓, the second constituent encoder 214 outputs the coded bits to its output port Yk,(M+1)/2. The systematic bits Xk mean actual transmission data, and the parity bits Yk are added to correct an error generated during decoding at the receiver. In FIG. 2, outputs of the first encoder 212 are represented, Yk,1, . . . , Yk,(M−1)/2, and outputs of the second encoder 214 are represented by, Yk,(M+1)/2, . . . , Yk,M−1. That is, as the mother code rate is increased to ⅓, ⅕and 1/7, output ports of the first and second constituent encoders 212 and 214 increase in number. The puncturer 216 is controlled according to a code rate determined by the controller 160. Specifically, the puncturer 216 selectively punctures the systematic bits or the parity bits according to a predetermined puncturing pattern, and outputs punctured coded bits Cn, thereby satisfying a predetermined code rate and modulation rate. That is, the puncturer 216 is provided with a predetermined puncturing pattern from the controller 160 according to the code rate, and punctures the coded bits output from the first and second encoders 212 and 214.
FIG. 3 illustrates a detailed structure of the first and second encoders 212 and 214 shown in FIG. 2. As illustrated in FIG. 3, the first and second encodes 212 and 214 each generally include a plurality of shift registers.
Referring to FIG. 3, the encoder encodes an input bit Xk into a systematic bit Xk and a parity bit Yk. The encoder can generate a different parity bit for the same input bit according to how the shift registers D and adders 302–305 are connected. Initial values of the shift registers D are all 0's, and outputs of the encoder with a mother code rate 1/M (M=3,5,7, . . . ) are X1, Y1,1, Y1,2, . . . , Y1,M−1, X2, Y2,1, Y2,2, . . . , Y2,M−, . . . , Yk,1, Yk,2, . . . , Yk,M−1, where k represents the total number of input bits. After encoding all input bits, a switch 301 in FIG. 3 is switched such that the coded bits are fed back to the shift registers D. The feedback coded bits are used as tail bits. Therefore, the encoder illustrated in FIG. 3 can generate 3 tail bits. As the channel encoder 120 is comprised of two encoders 212 and 214, the channel encoder 120 generates a total of 6 tail bits. The number of tail bits generated by the encoder is identical to the number of shift registers D comprising the encoder. If the 3 tail bits are applied to the first constituent encoder 212, the first constituent encoder 212 encodes the received tail bits, and then initializes the shift registers to their initial values 0's. The 3 tail bits generated by the second constituent encoder 214 are applied to the second constituent encoder 214, and the second constituent encoder 214 encodes the received tail bits, and then initializes the shift registers D. Meanwhile, the tail bits generated by the constituent encoders and the coded bits generated by encoding the tail bits are called TT (Trellis Termination) bits. If the two encoders with a mother code rate 1/M each include L shift registers, (M+1)×L TT bits are generated. The TT bits undergo puncturing or repetition by the rate matcher 130 along with the coded bits.
FIG. 4 illustrates a detailed structure of the rate matcher 130 shown in FIG. 1. As illustrated in FIG. 4, the rate matcher 130 is divided into a bit separator (or demultiplexer) 410, a bit collector (or multiplexer) 450, and rate matching processors 420, 430 and 440. FIG. 5 illustrates a general procedure for performing rate matching.
Referring to FIGS. 4 and 5, an input signal Cn from the channel encoder 120 is provided to the rate matcher 130. For the input signal Cn, the rate matcher 130 determines whether the number ΔN of bits to be punctured and repeated is a positive number or a negative number, and determines to perform repetition or puncturing according to the determined results (Step 512 of FIG. 5). That is, if the ΔN is a negative number, the rate matcher 130 punctures as many bits as the ΔN among the Cn. Otherwise, if the ΔN is a positive number, the rate matcher 130 repeats as many bits as the ΔN among the Cn.
For example, if the ΔN is a negative number, the Cn is provided to the bit separator 410. The bit separator 410 separates the input bits Cn into M bits S0 to SM−1. The S0 represents all systematic bits Xk among the input bits Cn. Here, the S0 may include a few of TT bits. The S1 to SM−1 represent Yk,1 to Yk,M−1, respectively. Each of the S1 to SM−1 may also include a few of TT bits. The S1 to SM−1 are provided to their associated rate matching processors 430 and 440, which determine the bits to be punctured according to a puncturing amount ΔNi (i=1˜N−1). A process of determining by the rate matching processors 430 and 440 whether to puncture each of the S1 to SM−1 is performed in steps 514 to 522 of FIG. 5. In most cases, the puncturing is performed on the parity bits rather than the systematic bits. Therefore, as illustrated in FIG. 4, the systematic bits S0 are provided directly to the bit collector 450 without separate rate matching. The bit collector 450 punctures the bits determined to be punctured among the coded bits provided from the rate matching processors 430 and 440, and outputs the non-punctured coded bits along with the systematic bits S0 provided from the bit separator 410.
However, if the ΔN is a positive number, bit repetition must be performed. Therefore, the input bits Cn are applied to the rate matching processor 420 where they undergo bit repetition. The rate matching processor 420 for bit repetition is applied to both the systematic bits and the parity bits, and this process is performed in steps 524 to 534 of FIG. 5.
The coded bits gr output from the rate matching processor 420 and the bit collector 450 are interleaved by the interleaver 140, and finally modulated by the modulator 150 before being transmitted to a receiver.
FIG. 5 illustrates a general procedure for performing rate matching. The parameters used in describing the rate matching operation with reference to FIGS. 4 and 5 include:
e: an initial error between a current puncturing rate and a desired puncturing rate;
eini: an initial value of the e;
eminus: a decrement of the e;
eplus: an increment of the e;
m: an index of a current bit;
δ: a value except 0 and 1 (a bit except 0 and 1 is punctured by the bit collector 450); and
D: the total number of bits applied to a rate matching algorithm
The parameters eini, eminus, and eplus are determined from the number ΔN of bits to be punctured or repeated, and the determining method is based on a rate matching technique defined by the 3GPP standard. The initial puncturing position are determined by the parameter eini.
Referring to FIG. 5, in step 510, the rate matcher 130 sets a parameter e to an initial value eini and sets a count value m to 1. In step 512, the rate matcher 130 compares the number ΔN of bits to be punctured or repeated with “0” to determine whether the ΔN is a positive number of a negative number. If it is determined in step 512 that the ΔN is a negative number, the rate matcher 130 performs a puncturing process through steps 514 to 522. Otherwise, if it is determined in step 512 that the ΔN is a positive number, the rate matcher 130 performs a repetition process through steps 524 to 530.
First, the puncturing process will be described in detail. In step 514, the rate matcher 130 compares a parameter m indicating the order of a bit to be currently processed with the total number D of input bits (m≦D), to determine whether the rate matching has been completely performed on all input bits. If it is determined in step 514 that the rate matching has been completely performed on all input bits, the rate matcher 130 ends the puncturing process. However, if it is determined in step 514 that the rate matching has not been completely performed on all input bits, the rate matcher 130 proceeds to step 516. In step 516, the rate matcher 130 updates the value e by calculating a difference e−eminus between the e and a decrement value eminus provided from an upper layer. After updating the e, the rate matcher 130 determines in step 518 whether the updated value e is less than or equal to “0.” If it is determined in step 518 that the updated value e is less than or equal to “0,” the rate matcher 130 proceeds to step 520 since the corresponding input bit is a puncturing bit. In step 520, the rate matcher 130 sets δ to a value except 0 and 1. Setting the δ to a value except 0 and 1 is equivalent to designating a bit to be punctured by the bit collector 450. Further, in step 520, the rate matcher 130 updates the e by calculating a sum e+eplus of the e and an increment value eplus provided from the upper layer. If the e is greater than “0” in step 518 or the operation of step 520 is completed, the rate matcher 130 increases, in step 522, the m by 1 to select the next bit, and then returns to step 514 to repeat the puncturing process.
Next, the repetition process will be described in detail. In step 524, the rate matcher 130 compares the m with the D (m≦D) to determine whether the rate matching has been completed. If it is determined in step 524 that the rate matching has been completed, the rate matcher 130 ends the repetition process. However, if it is determined in step 524 that the rate matching has not been completed yet, the rate matcher 130 proceeds to step 526. In step 526, the rate matcher 130 updates the e by calculating a difference e−eminus between the e and the eminus. After updating the e, the rate matcher 130 determines in step 528 whether the updated value e is less than or equal to “0.” If it is determined in step 528 that the updated value e is less than or equal to “0,” the rate matcher 130 proceeds to step 530 since the corresponding input bit is a repetition bit. In step 530, the rate matcher 130 repeats the corresponding input bit Si,m. Further, in step 530, the rate matcher 130 updates the e by calculating a sum e+eplus of the e and the eplus, and then returns to step 528 and compares again the updated value e with “0” thereby to determine whether the repetition must be performed again. That is, the rate matcher 130 repeats the corresponding input bit a predetermined number of times, through the steps 528 and 530. However, if the e is greater than “0” in step 528, the rate matcher 130 increases, in step 532, the m by 1 to select the next bit, and then returns to step 524 to repeat the repetition process.
As described above, in a transmitter for the conventional CDMA mobile communication system, the channel encoder and the rate matcher are separately constructed. In this case, one puncturing is performed by a puncturer in the channel encoder and another puncturing is performed again by the rate matcher, thus causing an increase in hardware complexity and a processing time and a decrease in performance of the channel encoder.